1. Field of the Invention
The present invention relates to a semiconductor memory device for transferring data via bit lines to write the data in a memory cell or to read out the same therefrom, such as a DRAM (dynamic random access memory) where a memory cell is provided in an element forming region on a silicon substrate or the like.
2. Description of the Prior Art
With the recent technical development toward higher density integration of semiconductor memory devices such as DRAMs, there is noticed of late the practical employment of a stacked capacitor type where the structure for storing data is formed into a stacked constitution to ensure a sufficient storage capacity. And a cell array of an open bit line system is also attracting considerable attention due to a high efficiency in reduction of the cell area and integration of the memory device itself.
In a conventional semiconductor memory device of stacked capacity type having a known open bit line structure, as shown in FIG. 1, impurity-diffused regions of switching elements Tr are formed on the surface of a silicon substrate 2 where a field insulating layer 1 is deposited, and a bit line 5 composed of an aluminum wiring layer is connected via a contact hole 4 to one source-drain region 3a of the impurity-diffused regaions, while a lower electrode 6 of each of stacked capacitors C is connected to another source-drain region 3b.
The lower electrode 6 of the capacitor is formed by patterning a second polycrystal silicon layer in a manner to reach, via an interlayer insulating film 8, an upper portion of a gate electrode (word line) 7 of the switching element Tr composed of a first polycrystal silicon layer. The capacitor lower electrode 6 has thereabove a capacitor upper electrode 9, which serves as a common electrode, via a dielectric film 10. And the stacked capacitor C is constituted of such stacked structure which comprises the capacitor upper electrode 9, the dielectric film 10 and the capacitor lower electrode 6. In this known example, one memory cell MC is composed of the switching element Tr and the stacked capacitor C formed on the silicon substrate 2.
In such semiconductor memory device, a required charge is stored in the stacked capacitor C, and data is read out from or written in the memory device via the bit line 5 under control by the switching element Tr. There is further shown a shunting (backing) metal wire 11 for reducing the resistance of the word line 7. Denoted by 12 is an interlayer insulating film of silicon dioxide or the like.
However, in such conventional semiconductor memory device, the following problems arise as a result of the technical progress toward higher density integration.
First, due to the necessity of achieving contact between the upper-layer bit line 5 and the source-drain region 3a, the capacitor lower electrode 6 and the capacitor upper electrode 9 constituting the stacked capacitor C need to be spaced apart from the contact portion between the bit line 5 and the silicon substrate 2. Accordingly there arises a disadvantage in that the capacitor-occupied portion in the memory cell MC is crowded which consequently causes difficulties in ensuring a sufficient capacity.
In addition, since the bit line 5 is existent in a state sandwiched between the capacitor upper electrode 9 and the metal wire 11, the bit line 5 interferes with the capacitor upper electrode 9 and the word line 7 at the charging or discharging time to thereby cause interference noise. And also when the voltage applied to the word line 7 is turned to a high level, there occurs interference noise in the bit line 5. Such interference noise is generated in regard to the bit line 5 which deteriorates the data, and the resultant disadvantage is conspicuous particularly in using the open bit line structure concerned with the subject of the present invention.
Further in the conventional semiconductor memory device, the distance m between the shunting metal wire, 11 and the silicon substrate 2 is increased since a plurality of wiring layers are sequentially superposed on the silicon substrate 2. Generally the shunting metal wire 11 is used also for connection to a peripheral circuit and so forth, and when the distance m between the metal wire 11 and the silicon substrate 2 is increased as described above, it becomes difficult in the peripheral circuit to attain a low-resistance contact between the metal wire 11 and the silicon substrate 2, hence deteriorating the irregularity covering facility for the metal wire 11.
Thus, it is necessary to realize a large-capacitance stacked capacitor in the open bit line structure while suppressing the inteference noise between the wiring layers so as to promote higher density integration of the memory devices.